The present invention pertains to methods for forming metal-derived layers on substrates. Particular methods apply to integrated circuit fabrication. Even more specifically, the invention pertains to selective methods for forming diffusion barriers on partially fabricated integrated circuits.
Modern manufacturing in the electronics industry relies heavily on thin film layers of various materials, particularly for integrated circuit (IC) fabrication. Some of these include diffusion barrier layers, anti-reflective layers, etch stop layers, dielectric layers, and the like. Many of these layers are made of metal or metal-derived materials.
Recently, copper is finding increasing use in IC fabrication for conductive pathways due to its excellent conductivity and electromigration resistance. However, copper readily diffuses into surrounding dielectric materials and degrades their insulating electrical properties. Hence, diffusion barriers are needed to protect adjoining dielectric materials from copper migration. Commonly, both conductive and nonconductive diffusion barriers are used in conjunction to encapsulate the copper routes.
Most notable among IC fabrication processes that use diffusion barriers in conjunction with copper inlaid conductive routes is Damascene processing. Damascene processing is often a preferred method because it requires fewer processing steps than conventional methods and offers higher yields. It is also particularly well suited to metals such as copper, which cannot readily be patterned by plasma etching. During a Damascene process in IC fabrication, a pre-formed dielectric layer (for example silicon dioxide) is etched in order to form line paths (trenches and vias). These surface features will ultimately be filled with copper inlay to form conductive routes. As mentioned previously, copper can readily migrate into the adjoining dielectric regions under the influence of thermal and electrical gradients. Hence, before copper can be deposited, the dielectrics must first be protected with a diffusion barrier. Typically an electrically conductive barrier layer is used in the via and trench features. Suitable materials for electrically conductive diffusion barriers include tantalum, tantalum nitride, tungsten, titanium, titanium tungsten, and titanium nitride, to name a few.
Typically, diffusion barriers are formed by deposition methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Using these methods, a conductive diffusion barrier is layered over the surface of a wafer (including the vias and trenches) and a copper layer, to serve as seed for the next step, is deposited thereon. The wafer is transferred to an electrochemical bath for an overcoat of copper that will also fill the vias and trenches. Subsequently, chemical-mechanical planarization techniques are applied to remove the copper overcoat, leaving copper in the vias and trenches alone. After the copper inlay is in place, a non-conductive diffusion barrier (e.g. silicon nitride or silicon carbide) is deposited over the field surface of the wafer to encapsulate the copper routes. In subsequent processing, when a newly laid dielectric layer is etched to form another series of via and trench features, the non-conductive diffusion barrier is etched through to reveal the underlying copper conductive routes. Another conductive diffusion barrier is deposited, followed by another layer of copper inlay, and another non-conductive diffusion barrier. This process is repeated forming layers of electrically connected, but encapsulated, copper conductive routes. Thus, in the final structure there is a conductive diffusion barrier between adjoining copper conductive routes.
Although diffusion barriers can be broadly categorized as conductive and nonconductive, the materials (mentioned above) used for conductive diffusion barriers are often ten to one hundred times less electrically conductive than the copper routes that they encapsulate. Such diffusion barriers are sufficiently conductive for conventional circuitry, however, with the continuing need for faster signal propagation and reliable microchip circuitry, the electrical resistance of conventional diffusion barriers made of the materials mentioned above is problematic.
What are therefore needed are selective methods for forming metal-derived layers on substrates. More specifically, methods are needed for forming metal-derived layers on integrated circuit structures. Even more specifically, selective methods are needed for forming barrier layers on integrated circuit structures, methods in which the diffusion barrier is formed only on dielectric surfaces and not on metal surfaces. In this way, process sequences are shortened and the resistance between inlayed metal conductive routes is reduced.
The present invention pertains to selective methods for forming metal-derived layers on substrates. Preferred methods apply to integrated circuit fabrication. In particular, selective methods of this invention may form diffusion barriers on partially fabricated integrated circuits. In one preferred method, a wafer is heated and exposed to a metal vapor. Henceforth, a reference to metal vapor implies neutral metal atoms, metal ions, or combinations of the two. Under specific conditions, the metal vapor chemically reacts with dielectric surfaces to form a diffusion barrier, but does not react with metal surfaces. Thus, methods of the invention form diffusion barriers that selectively protect dielectric surfaces but leave metal surfaces free of diffusion barrier.
Thus, one aspect of the invention pertains to a method for forming a metal-derived layer on at least a portion of a substrate. Such methods may be characterized by the following sequence: heating the substrate; and exposing the substrate to a metal vapor under a set of conditions in which the metal vapor chemically reacts with at least a portion of the surface of the substrate to form the metal-derived layer thereon, the metal-derived layer being non-volatile under the set of conditions. Preferably the set of conditions includes a flux of metal vapor and a substrate temperature such that the evaporation rate of metal from the substrate is equal to or greater than the deposition rate of the metal on the wafer substrate. Hence, there is no net build-up of metal on the wafer substrate, but accompanying reactions yield a metal-derived layer selectively on at least a portion of the wafer substrate.
In some preferred methods of the invention, the substrate is a partially fabricated integrated circuit and the metal-derived layer is made of at least one of a metal-oxide, a metal-carbide, a metal-nitride, a metal-silicide, a metal halide, and combinations thereof. For methods of the invention that pertain to integrated circuit fabrication, the substrate temperature is preferably between about 50 and 1000xc2x0 C., more preferably between about 200 and 400xc2x0 C. For IC fabrication, preferably metal vapors are formed by a physical vapor deposition (PVD) technique such as evaporation, sputtering, etc. In a particularly preferred embodiment, the PVD technique is magnetron sputtering. As would be understood by one skilled in the art, single metals or combinations of metals can be used to form metal vapors, especially using the above mentioned PVD techniques. Preferably the metal vapor of the invention includes at least one of magnesium, aluminum, zinc, cadmium, calcium, tin, and strontium.
Even more specific to integrated circuit fabrication, another aspect of the invention pertains to a method for selectively forming a diffusion barrier on a wafer substrate having a plurality of dielectric surfaces and a plurality of metal interconnect surfaces. Such methods may be characterized by the following sequence: heating the wafer substrate, and exposing the wafer substrate to a metal vapor under a set of conditions in which the metal vapor chemically reacts with the plurality of dielectric surfaces to form a non-volatile barrier material thereon, and the metal vapor does not react with the plurality of metal interconnect surfaces. Preferably the set of conditions includes a flux of metal vapor and a wafer substrate temperature such that the evaporation rate of deposited metal from the substrate is equal to or greater than the deposition rate of the metal vapor on the wafer substrate. This aspect of the invention pertains particularly to Damascene processing, preferably with copper interconnects.
Dielectric surfaces to which the invention is applicable preferably include at least one of silicon dioxide, silicon nitride, silicon oxynitride, fluorinated silica glass, CORAL(trademark) from Novellus Systems, Inc. of San Jose, Calif., Black Diamond(trademark) from Applied Materials, Inc. of San Jose, Calif., SiLK(trademark) from Dow Corning, Inc. of Midland, Mich., and Nanoglass(trademark) of Nanopore, Inc. of Albuquerque, N.Mex. Preferably the diffusion barriers formed on integrated circuit substrates are made of the non-volatile barrier material that is between about 10 and 200 xc3x85 thick.
In particularly preferred methods, the metal vapor is produced in an energized plasma, and the metal is magnesium. In these methods, the wafer substrate temperature is between about 200 and 500xc2x0 C., more preferably about 400xc2x0 C. The non-volatile barrier material formed in these methods will include at least one of magnesium oxide, magnesium silicon oxide, magnesium nitride, and magnesium silicate. Preferably, these magnesium-based non-volatile barrier materials formed are between about 10 and 100 xc3x85 thick.